1. Field
One embodiment of the invention relates generally to a memory system and a memory device for use in various kinds of electronic apparatuses, and more particularly to a memory system and a memory device which are so improved as to flexibly adaptable to the expansion in memory size.
2. Description of the Related Art
In general, in a memory system which is composed of memory devices such as DDR SDRAMs, a bus (data bus, command bus, address bus) is shared by a plurality of memory devices. A chip select signal is allocated to a unit of each individual memory device or to a unit of memory devices. A controller (memory controller) selectively asserts the chip select signal, thereby being able to select one device or one set of devices.
In the memory system in which the bus is shared by a plurality of memory devices, however, as the number of memory devices which are connected to the bus becomes greater, the load on the bus increases. Thus, if many memory devices are connected to the bus in order to expand the memory size of the memory system, the signal quality of, e.g. a data signal, an address signal and a control signal degrades, and the operational reliability may possibly deteriorate.
Recently, there has been developed a memory device which supports point-to-point data interconnection, thereby to realize a high data transfer speed (see, e.g. “Dynamic Point-to-Point Technology”, available online at Rambus Inc.
In addition, an XDR™ DRAM is known as a memory device which supports point-to-point data interconnection. The XDR™ DRAM includes a plurality of data pins which are point-to-point connectable to a controller. The XDR™ DRAM also includes a function called “Dynamic Width Control”, and only some of the plural data pins can be used for data transfer with the controller. In this case, the other data pins remain unused.
However, in the XDR memory system, although data lines are independent in association with each individual memory device, a control signal line for transferring an address signal and a command signal are shared between a plurality of memories. Thus, if a memory device is additionally provided in order to expand the memory size, it is possible that the signal quality of the address signal or command signal deteriorates.
It is necessary, therefore, to realize a novel function which is flexibly adaptable to the expansion of memory size, without causing degradation in signal quality.